Generator of different patterns of time-sequential pulses



Dec' 22 1964 l.. L.. RAKoczl ETAL 3,162,816

GENERATOR OF' DIFFERENT PATTERNS OF TIME-SEQUENTIAL PULSES 5Sheets-Sheet 1 Filed Jan. 27, 1961 Q N m Q Q u .n

Dec. 22, 1964 1 RAKoczl ETAL 3,162,816

GENERATOR 0F DIFFERENTIPATTERNS 0FY TIME-SEQUENTAL PULsEs Filed Jan. 27.1961 3 Sheets-Sheet 2 INVENTOR /ifzzo Z, @www l y By we /M Pia/i777 De22, 1964 L. L.. RAKoczl ETAL 3,162,816

GENERATOR OF' DIFFERENT PATTERNS OF' TIME-SEQUENTIAL PULSES 3Sheets-Sheet 3 Filed Jan. 27, 1961 United States Patent O 3,162,816GENERATOR F DWFERENT PATTERNS 0F TllVIE-SEQUENTIAL PULSES Laszlo L.Rakoczi, Merchantville, NJ., and Lino M.

Paoletti, Philadelphia, Pa., assignors to Radio Corporation of America,a corporation of Delaware Filed ian. 27, 1961, Ser. No. 85,265 6 Claims.(Cl. 328-63) This invention relates to a new and improved circuit forgenerating pulses both of fixed and controllable duration. The inventionis useful, among other places, in data processing equipment; and thecircuit for generating pulses of controllable duration find specialapplication in asynchronous digital computers. The invention is relatedto the apparatus described in Paoletti and Rakoczi, Patent No.3,107,332, dated October l5, 1963, based on application Serial No.31,335, tiled May 24, 1960.

An objective of the invention is to provide a highly versatile controlpulse generator which is suitable for use in data processing equipment.

Another objective of the invention is to provide a control pulsegenerator which is capable of asynchronous pulse generation, that is,which can produce pulses of a duration dependent upon the times requiredby various circuits in a digital computer to perform their functions.

The control pulse generator of the invention generates different groupsof pulses in response to different patterns of control signalsrepresentative of binary digits applied to the generator. These controlsignals may be returns from the computer itself which indicate to thecontrol pulse generator the desired pattern of control pulses to beproduced as a consequence of the results of certain operations performedby the computer. As one example, the values of the control signals maybe determined by the signs of two words being added. Under one set ofcircumstances, the generation of a group of control pulses is requiredwhich direct the computer to perform one form of binary addition and,under another set of circumstances, the generation of a group of controlpulses is required which direct the computer to perform another form ofbinary addition.

The invention is described in greater detail below and is illustrated inthe following drawing in which:

FIGURE 1 is a block circuit diagram of a synchronous control pulsegenerator according to the present invention;

FIGURE 2 is a sketch showing various patterns of pulses which can begenerated by the circuit of FIG- URE l;

FIGURE 3 is a block circuit diagram of circuits which generate thecontrol signals for the circuit of FIGURES 1 and 4; and

FIGURE 4 is a block circuit diagram of an asynchronous pulse generatoraccording to the present invention.

Throughout the gures, similar reference characters are applied tosimilar elements.

The individual blocks shown in the figures above are in themselves knowncircuits. The circuits of the blocks are actuated by electrical signalsapplied to the blocks. When the signal is at one level, it representsthe binary digit 1 and when it is at another level, it represents thebinary digit 0. For the sake of the discussion which follows, it isassumed that a high level signal represents the binary digit l and a lowlevel signal the binary digit 0. Also, to simplify the discussion,rather than speaking of an electrical signal being applied to a block orlogic stage, it is sometimes stated that a l or a 0 is applied to theblock or stage.

Throughout the figures, a logic circuit known as a multiple-input nonegate (sometimes also known as a nor gate) is used. A none gate producesa l output when all of the inputs of the gate are 0, and a 0 output whenCCv one or more of the inputs are 1. This gate may consist of aninverter connected to each of the input leads to an and gate.Alternatively, a nonegate may consist of an or gate followed by aninverter. The Boolean equation for a none gate having A and B inputs anda C output is F=C or A+B=C, and the truth table for the gate is:

The ilip-ops shown in the various iigures are also conventional;however, the output connections are reversed from those usually shown.Thus, when a flip-flop is set, the barred or 0 output of the flip-opbecomes l and the unbarred or the 1 output of the flip-ilop becomes "0.Conversely, when the flip-flop is reset, the unbarred or 1 outputbecomes 1 and the barred or 0 output becomes $0.,

The circuit shown in FIGURE 1 is capable of producing 13 differentcontrol pulses. These are produced by 13 none gates legended 1-13,respectively. The output terminals of the none gates are connected toset or reset connections of various flip-flops. Three such ip-ilops 14,15 and 16 are shown. The barred and unbarred output terminals of theip-ops are connected in various diterent ways to the input terminals tothe none gates, however, no none gate receives inputs from a ip-ilop towhich it supplies an output. For example, the iiip-ilop outputs to nonegates 6-9 are AD, KD, AD `and D, respectively. These none gates do notreceive B or E inputs. Similarly, the dip-flop inputs to none gates 1,2, 4 and 5 are BD, E, BD and ED. These none gates do not receive A orinputs.

In addition to the above, various control signals are applied to thenone gates. These are in the form of direct current levels. A controlsignal T, which may be manually applied or which may come from thecontrol unit of the computer and is applied to none gate 2, starts thepulse generator operating. The control signals Ll-L.,z which may bemanually introduced or which may come from the control unit of thecomputer, determine the pattern of control pulses which are produced, asis explained in more detail later.

Certain of the control pulses are applied as'inputs to none gate 17. Theoutput terminal of this none gate is connected through delay line 18 toseries-connected inverters 19 and 20. The output of inverter 19 is aControl signal E and the output of the inverter 20 is a control signalP. These signals are applied as inputs to the none gates in the mannershown in the ligure. Each group of pulses applied to the none gates isunique.

From a logic standpoint, inverter 20 may be omitted and the P signalobtained from the lead between delay line 1S and inverter 19. However,this would mean that only part of the power available at the output ofthe delay line could be used to drive Athe none gates (since the otherpart of the power would be applied to the inverter 19). In a particularpulse generator for which the circuit of FIGURE 1 (and the circuit ofFIGURE 4) is designed, a greater amount of pulse P power is desired andit is for this reason that the additional inverter stage 20 is employedto obtain P. v

For the present, it may be assumed that the control signals L1L4, eachof which represents a binary digit,

represent the binary digit ilf Control signal T alsoV initiallyrepresents the binary digit 1. The ip-ilops 14, 15 and 16 are allinitially reset so that the unbarred output of each of the dip-hops is land the barred output is 0.15 1-13 have at least one 1 applied at aninput terminal and accordingly allA none gates are inactivated.Therefore, all of the C outputs of the none gate represent the binarydigit 0. This means thatno control pulses are present.

To start the pulse generator of FGURE 1, T is changed from l to 0. Itmay also he assumed for the present that L1 is changed from l to 0 andL2:L3:L1:1. Under these conditi-ons, none gate 2 is actuated since thefour inputs to the none gate T, are all 0. is because all of the inputsto none gate 17 are 0. This produces a 1 output at none gate 17 which isinverted in stage 19 to produce "P:0.?

When none gate 2 is activated, control pulse C1V is generated. Thiscontrol pulse sets dip-flop 14 changing A to 0 and to 1. Control pulseC1 is also applied to none gate 17, changing the output of none gate 17from l to 0. After a time equal to the delay induced by delay liuc 18,change-Sirolo 0 to l and P changes from 1 to 0. The time delay may be ofthe order of one or more microseconds and is equal to the duration of.each pulse .C-

After the delay interval Speed above, the inputsV t0, none gate 6 areal1 0. A is 0 by virtue of the setting of flip-dop 14 by control pulseC1. is 0 as dip. flopl 16 is reset. P is 0 as the output of none gate 17is 01, The activated none gate 6 produces conf trol pulse C1. Thiscontrol pulse sets flip-dop' 1:5, chang'-y ing 1 3. to l and B to.. 0.is one of the inputs to none gate 2, andv when changes to 1, none gate Zis again inactivated. Accordingly, the start of control' Pulse C2Signals the'nd of control' nuls@ C1.,

Ij is also one of the inputs to none gate 2. "I" changes t0 1 at the @ad0f the delay line interval, Thus, this signal, F:1, also insures that C1ends when C2 starts and insures that the C1 and C2 pulses do notoverlan- Trseer signal T:0. may be terminated any time after the end ofcontrol pulse C1. For example, it may change to 1":1 at the end of pulseC2 as Shown` chart A below.

The analysis of the circuit above can be continued in the manner setforth, and if this is done, it isfound that` for the pattern of controlsignals 1.1-1.4 given, a first group of pulses C1-C8 is generated. L1may be changed from 10, to l when control pulse C1 is generated. Thismay be done manually or by a circuit discussed later. The purpose is tobe ready to start the next cycle of pulse generation A second group ofoutput pulses may be generated by' the circuit of FTGURE 1 if adifferent pattern of control signals L1-L4 is applied. When :the patternis L1:l, 222:0, L3:1, L1: 1, the control pulses produced are C1, C2, C9,Cm, C11 and Ca in that Sequence. 1.11 this group of pulses, when C111 isgenerated, control pulse L1 changes from l to 0. This can be donemanually or by a circuit discussed later. During the generation of thisgroup of pulses, C1 and C2 are produced in exactly the same Way asdiscussed above. When pulse C2 starts, the circuitrconditions are T:0,14:0, B:0,`` D:1, L1:1,

L2:O, L;1:1, 151:1, P:0 and "P`:1. After a time equal' to the delay lineinterval, changes to 0 and P- changes to 1. Now the conditions are suchas to activate none gate 10 and no other gate. This gate has as itsinputs L2, A, Band allot which are 0. Accordingly,

Under these conditions, all `of the noue gates none gate 10 producescontrol pulser C9. This control pulse sets :dip-flop 16, changing to 1.As l5 and P, both of which are now 1, are inputs to none gate 6 whichproduces control pulse C2, none gate 6 is inactivated and pulse C2 isterminated.

Control pulse C9 is one of the inputs to none gate 17. Accordingly,after a delay equal to the delay irnparted by delay line 18, changes to1 and P changes to 0. The conditions are now appropriate for generationof control pulse C111 by vnone gate 3, as all of the inputs to none gate3 are now 0. Control pulse C10 resets ipeflop 14, changing A. from 0to' 1. A and are the inputs to none gate 10A which produces controlpulse C9; Accordingly, the star-t of control pulse .C10

signals .the end of controlv pulse C9.

The circuit operation for control pulse C11 and C1,Y of

the second group is similar to that already discussed and can be easilyfollowed. The oper-ation is outlinedin the charts which follow. Togenerate C11, L4must be changed' from 0 to l during the interval ofpulse C10. Again, this may be done manually or by the circuit discussedlater. During the interval of C8, L1 is changed from $07, $1.7

A thirdv pattern of controlV pulses can be produced' from the circuit ofFIGURE l by again changing the coding of the control signals L1'-L,1.When L1: 1, L2:0, 1.3:1v and L.1\:1, the generator starts to generatevpulses like those ofthe second' group, namely C2, C9 and C10. If, duringthe time C10 is generated, L3 is changed from l to 0 so that thepatternof Ls is L1:-l', L2:0, [13:0` and L1: l', the pulses C112 andC13are generated. During the interval of C12, L2 'changesfr'om' 0 to 1.yThe circuit operationcaneasily be traced in the manner outlined' above.

The circuit operation discussed above for the three groups of pulses isgiven succinctly in- Chart A below.

In this chart, loop 1 corresponds? to the iirst group of pulses (E1-C11;loop 2 corresponds to the secondV group of pulses C1, C2,C9, C19, C11,C3; and loop 3 corresponds fov the third group of pulses c1, C2, og, Cm,C12, C13.

CHAR'FA Loopl '1` a n D L1 L1 V1.1 Li P PULSE 1 1 'a V1 v 1M n 1A i VVi1 1 o Non@ o o 1 1 o 1 o s 1 i 1 1 o C1 on' 1 1'1'c`0`-1 1 1 VoV 1 VCi 11 Vo 0 "1' i '0` '0Vv i "1' 1' 1 'c VCi 1 1A o a 1 o 1 u 1 1 1 o 1 oiV1'o` 1 c? 1 di r6'1"'1'1' 1 'ofV ho; i

1 o 1 1 o Q 1 v 0 i 1 1 0 1A C1V 1 1 o 1 o o 1 1 1 r1 1 1 o G1 1 1 u iAo 1 0` 1'1"1j1 0'7'1 "Ci LoopZ '1 A K B is" D i5 L1 L1 La L4 P PULSE 1 10 1 o 1 o 1 1 i 1 1Y 0"' None o o 1V 1V o 1 ol '1'0 i '1' 1" o o1 1 o 1o- 1 1 o' 1 n YY1 `1` 1 01' 1 o 1 o 1 s 1 1 o 1 1 1 o o1V 1 1 0- o- 1vo- 1 1 d 1 o `o' 1 om 1 1V o 1 o vo 1 1 n 1v o 1 0 C 1 1 o 1 o 1 o 1 1 11 o `1 o1 1 1 o 1 o 1 o i1 Y1 -1 i 1V d None Loop 3 '1 A K B 'E D 15 L,Li La* L1 P PULSE o o 1 1 o 1 o 1 o 1 1 1 o C1 o o 1 o 1 1 o 1 o 1 1 0 1C2 1 o 1 o 1 o 1 1 o 1 1 1 o C 1 1 o o 1 o 1 1 o o 1 1 o om 1 1 o o 1 1o 1 1 o 1 1 o on 1 1 o 1 o 1 o 1 1 o 1 o 1 C11 1 1 o 1 o 1 0 1 1 o 1 1 oNone La is reset by C1.

pulses inthe various loops is given in Chart B below:

If the binary digit generated at the 1 terminal of hip-Hop is 1, thepulses in loop 1 are generated. If the binary digit generated at the 1terminal of the hip-Hop 40 is 0, then either the pulses in loop 2 or 3are generated.

In operation, ip-flops 42, 44, 52 and 54 are all initially reset.Control pulses C generated in previous cycles perform the resetting. Ifthe binary digit produced at the 1 output terminal of iiip-iiop 40 is 1.and the digit produced at the O terminal is 0, none gate 36 isdisabled, and none gate 38 is enabled. If now T is made 0, instructingthe pulse generator to start, none gate 38 produces a l output and ip-op44' is set. This means that L1 becomes 0 and L2 remains 1.

Flip-flops 52 and S4 of FIGURE 4 are also initially reset. Therefore, L3and L4 are 1. Thus, the values of L1-L4 are such that the generation ofpulses in loop 1 begins. As can be seen from FIGURE 3, pulse C7 is ap'-CHART B L1 L2 L3 L4 PULSES REMARKS 0 1 1 1 C -C7 L1 changes from 0" to lduring C1. Loop 1 1 0 1 1 C1, C2, C

Loop 2 1 0 1 0 Cm, Cn L1 changes from 1 to O during C10.

1 1 1 1 C@ L4 changes trom 0 to 1 and La from O to 1 durlng Cs.

1 0 1 1 C1, C2, C9,

Loop 3 1 0 0 1 C10 L3 changes from 1 to 0" during C10.

1 1 0 l C12, C13 L2 changes from 0 to 1" during C12.

The generation of the three different groups of pulses in the circuit ofFIGURE 1 is shown diagrammatically in FIGURE 2. The binary digits givenare the unbarred outputs A, B and D of the three flip-hops 14, 15 and16, respectively. It is of interest to note that the binary numberschange only one binary digit at a time, just as in the Gray code, forexample.

The circuit of FIGURE 1 is a synchronous control generator. In otherwords, each of the output pulses is of the same duration, and thisduration is determined by the length of delay line 1S.

FIGURE 3 shows, in brief form, the circuit for generating the controlsignals L1-L4. The circuit includes flip-flop iti which may be, forexample, one of the iiipflops in the instruction register of a largescale digital computer. The l output of the hip-flop is one input tonone gate 36 and the 0 output is one input to none gate 38. These nonegates also receive the T or trigger input which commands the pulsegenerator of FIGURE 1 to start producing pulses. The output of none gate36 is applic to the set input terminal of a ip-tlop 42 and the output ofthe none gate 38 is applied to the set vinput terminal of a dip-flop 34.These iiip-ops produce the L2 and L1 control signals, respectively.

Block Si? at the upper right is a circuit for performing a logicoperation on words transferred to it `from registers such as 51 and 53.Each register has multiple output leads, however, they are representedin the drawing as a single bus for the sake of drawing simplicity. Forexample, block may be an adder-subtracter and the operation it is toperform may depend upon whether the signs (plus or minus) of the wordsoperated on are like or unlike. One output of the logic circuit Sti isconnected to iiip-op 52 which produces the L3 control signal and anotheroutput isconnected to the dip-flop 54 which produces the L4 controlsignal. Other outputs of the circuit 50 at which the output word isavailable are not shown.

The binary digit generated at the 1 output terminal of the nip-flop 4()determines whether the pulse generator is to generate the pulses in loop1 or those of loops 2 or 3.

plied to the reset terminal of Hip-flop 44. This changes L1 to 1 asindicated in Chart A. Pulse C8 is applied to the reset terminal ofiiip-iiop 42. However, L2 is already l so that pulse C8 has no effect.

When the 1 output of fiiplop 4t) (FIGURE 3) is a 0, gate 35 is enabledand gate 38 is disabled. The T=0 pulse now causes the none gate 36 toset ipflop 42. The pattern of L pulses is now L1=1, L2=0, L3=1, L4=1.This is the pattern required for the generation of pulses in loop 2 andloop 3. Control pulses C1, C2, C9 and C10, in that order, are common toboth loops.

The control pulse C10 is applied to the logic circuit Sii. Under one setof operating conditions, the circuit S0 produces an I=1 output which isapplied to the set terminal of iip-iiop 54. This changes L4 from l to 0,whereby the generator produces pulses C11 and C8 after pulse C10. Theseare the pulses of loop 2 as may be seen from charts A and B above. PulseC8 resets ip-op 54 changing L4 back to 1, and resets flip-dop 42,changing L2 back to 1. Thus, all ip-ops 42, 44, 52 and 54 are reset andready for the next cycle.

Under another set of operatingconditions, when pulse C10 is applied tologic circuit 50, G=l is produced. This sets iiip-op 52 and L3 changesfrom l to 0. Now the pulses C12 and C13' of loop 3 are generated. PulseC12 resets ip-1iop 42, changing L2 to 1. Pulse C1 in the next cycleresets flip-nop 52.

The control pulse generator shown in FIGURE 4 is in many respectssimilar to the. one of FIGURE 1. The principal dilerence is that thepulse generator of FIG- URE 4 is a synchronous-asynchronous pulsegenerator. In other words, some of the pulses it produces are of fixedduration and others are of controllable duration. Put another way, theduration of some of the control pulses is controlled by the delayimparted by delay line 18, and the duration of other control pulses isdetermined by the length of time required to perform the operationcommanded by the control pulse.

In the example chosen for illustration, the operation commanded isaddition. Control pulses C3, C7, C9 and C12 are the ones which commandaddition. In each case when the addition is completed, the adder, shownas block 56 at the lower left, produces an output pulse RT. This outputpulse in each case is applied to the gate which produces the followingpulse. For example, RT is applied to none gate 11. Thus, when theaddition is completed and RT changes from l to fVO," none" gate 11 isactivated and control pulse4 C4' starts. Control pulse C4 setsiiip-op16, changing to 1. is one of the inputs to none gate 4 which producescontrol pulse C3. Accordingly, none gate 4 is inactivated and controlpulse C3 is' terminated. In a similar manner, control pulses C7, C9 andC12 are all of controllable duration.

What is claimed is:

l. In a pulse generator, a plurality of multiple input logic gates, eachgate for. producing' an output pulse in response to a given pattern ofinput signals applied to said gate; a plurality of ip-iiops, each with aset and reset input terminal and zero and one output terminals; aconnection from the output of each gate to one of the set and resetinput terminals of a flip-flop, and input connections to each gate fromoutput terminals only of Alip-lops other than'the one to which itsoutput is connected, each gate receiving not more than one input fromeach liip-ilop; circuit means connected to lreceive the outputs of atleast some of said gates for applying an enabling signal to other ofsaid gates; and means for applying different patterns of a plurality ofcontrol signals to a group of said multiple input logic gates forproducing different groups of time sequential output pulses from saidgenerator.

2. In a pulse generator, a plurality of multiple input logic gates, eachgate for producing an output pulse in response to a given pattern ofinput signals applied to said gate; a plurality of iiip-ops, each with asetl and reset input terminal and zero and one output terminals; aconnection from the output of each gate to one ofthe set and reset inputterminals of a flip-flop, and input connections .to each gate fromoutput terminals only of flip-Hops other than the one to 'which itsoutput is connected and notfrom nip-flops to which its output isconnected, each gate receiving not more than one input from eachtlip-lioip; circuit means connected to receive the outputs of at leastsome of saidgates for applying enabling signals some of fixed and someof controllable duration to other of saidv gates; andl means forapplying different patterns of n control signals to a group of saidmultiple input logic gates for producing different groups of outputpulses intime. sequellcer from said generator where n is an integergreater than one.

3'. In a-pulse generator, a plurality of multiple input none gates,eacliY gate for producing an output pulse in response, to a givenpattern of input signals applied to said gate; a plurality of ip-ops,each With a set and reset input terminal and,l zero and one outputterminals; a connection from the output of each gate yto 'one of the setand reset input terminal-s of a; flip-flop, and input connections toeachzgat'e from output terminals only of iiipops; other than the.V oneto which its output is connected, eachj gate receiving not more than oneinput from each flip-flop; circuit means connected to receive theoutputs of at least some of said gatesl for applying enabling signals,some o fixed and some of controllable duration, to other of said gates;and; means responsive to certain oi the pulses' produced by the gatesfor changing the values of the control signals appliedrto a group ofsaid multiple input none gates' for changing the pattern of outputpulsesproduced in time sequence by said generator.

4f. In a pulse generator, a plurality of logic gates, each having aplurality of input terminals and an output terg .Y minal, each gate forproducingv at its output terminal a diierent control pulse; a pluralityof flip-flops, each receiving control pulses from diiere'nt ones of saidoutput terminals as set and reset voltages for said flip-deps; acircuit, including a delay line, to which a plurality of said controlpulses are applied for producing delayed control pulses and inverteddelayed control pulses; means for applying a group of control signals tosome vof said gates, not more than one control signal to a gate, forproducing idifrerent patterns of output pulses from the gates; means forapplying saiddelayed control pulses vand said inverted delayed controlpulses to said gates, not 'more than one to a gate; and means forapplying t each gate the outputs of flip-Hops other than the one towhich the gate output :terminal is connected, each gate receiving notmore than one input from each flip-flop.

5. In a pulse generator, a plurality of none gates, each having aplurality of input terminals and an output terminal, each gate forproducing at its output terminal a different control pulse; a pluralityof ip-ilops, each receiving control pulses from diierent ones of saidoutput terminals as set and reset voltages for said ip-ops; a circuit,including a delay line, to which a plurality of said control pulsesarerapplied for producing uninverted delayed control pulses and inverteddelayed control pulses; means for applying said uninverted delayedcontrol pulses land said inverted delayed control pulses to said gates,not

' more than one delayed control pulse to a gate; means for applyingto'each none gate the output of llip-ops other than the one to which thegate output terminal is connected, each none gate receiving'differentcombinations of said liip-op outputs andrdelayed control pulses; andmeans for applying a group of control signals, not more than one signalto a gate, to a group of said none gates, for controlling the pattern ofcontrol pulses produced by the none gates.

` 6. In a pulse generator, a plurality of logic gates, each having aplurality of input terminals and an output terminal, each gate forproducing at its output terminal a ditferent control pulse; a pluralityof flip-Hops, each receiving control pulses from dilere'nt ones of saidoutput terminals as set and reset voltages for s'aid flip-Hops; av

first circuit, including a delay line, to which a plurality of saidcontrol pulses are applied for producing uninverted delayed controlpulses and inverted delayed control pulses;

an asynchronous circuit to which at least one of the con- V trol pulsesnot applied to said lijst circuit is applied, for producing a controlsignal which is delayed a variable amount of time; means for applyingsaid uninverted'delayed control pulses and 'said inverted delayedcontrol pulses to said gates, not more than one to a gate; means forapplying said'variably delayed control signal to at least one of saidgates; means for applying to each gateV the outputs `of flip-flops otherthan the one to Which the gate output terminal i's connected, each gatereceiving different combinations of said flip-flop outputs and delayedcontroly pulses; and means Vfor applying a group of control signals, not'more'than one signal to a gate, to a group of said logic gates, forcontrolling theY pattern of control pulses produced by said logicgates.v

References Cited by the Examiner UNTTED STATES PATENTS 3,107,332 10'/ 63Paoletti et al. a Y328-63 OTHER REFERENCES Handbook of Automation,Computation and Control, vol. II, by Grabbe, Ramo and Woolridge, JohnWiley & Sons, Oct. 12, 1959, pages 17-01 to 17-32.

ARTHUR GAUSS, Primary Examiner. RVING L. SRAGOW, Examiner.

1. IN A PULSE GENERATOR, A PLURALITY OF MULTIPLE INPUT LOGIC GATES, EACH GATE FOR PRODUCING AN OUTPUT PULSE IN RESPONSE TO A GIVEN PATTERN OF INPUT SIGNALS APPLIED TO SAID GATE; A PLURALITY OF FLIP-FLOPS, EACH WITH A SET AND RESET INPUT TERMINAL AND ZERO AND ONE OUTPUT TERMINALS; A CONNECTION FROM THE OUTPUT OF EACH GATE TO ONE OF THE SET AND RESET INPUT TERMINALS OF A FLIP-FLOP, AND INPUT CONNECTIONS TO EACH GATE FROM OUTPUT TERMINALS ONLY OF FLIP-FLOPS OTHER THAN THE ONE TO WHICH ITS OUTPUT IS CONNECTED, EACH GATE RECEIVING NOT MORE THAN ONE INPUT FROM EACH FLIP-FLOP; CIRCUIT MEANS CONNECTED TO RECEIVE THE OUTPUTS OF AT LEAST SOME OF SAID GATES FOR APPLYING AN ENABLING SIGNAL TO OTHER OF SAID GATES; AND MEANS FOR APPLYING DIFFERENT PATTERNS OF A PLURALITY OF CONTROL SIGNALS TO A GROUP OF SAID MULTIPLE INPUT LOGIC GATES FOR PRODUCING DIFFERENT GROUPS OF TIME SEQUENTIAL OUTPUT PULSES FROM SAID GENERATOR. 